1. Field of the Invention
The present invention relates to a timing generator which generates a test periodic signal of a whole testing device or a timing pulse signal for matching a test timing, and a semiconductor testing device provided with this timing generator.
2. Description of the Related Art
Prior to the description of the present invention, the outline of a conventional semiconductor testing device will be described with reference to FIG. 5.
In a semiconductor testing device 1 in which a semiconductor integrated circuit (device under test: DUT) 10 is a test object, as shown in FIG. 5, a major constitution comprises a test processor (not shown) which controls an overall procedure of the semiconductor testing device 1; a pattern generator 11 which generates a test pattern, an expected value pattern and the like; a waveform formatter 12 which formats the test pattern from the pattern generator 11 into a test signal waveform to send the waveform to the DUT 10 via a driver 14; a pattern comparator 13 which logically compares a test result sent from the DUT 10 via a comparator 15 with the expected value pattern from the pattern generator 11 to detect agreement (match) and disagreement (mismatch) and to judge whether or not the DUT 10 is satisfactory; and a timing generator 20 which generates a timing pulse signal and which supplies the timing pulse signal to the waveform formatter 12, comparator 15, pattern comparator 13 and the like to take a test timing.
As shown in FIG. 6, the timing generator 20 has a period generating section 21 which determines the test period of an overall system of the semiconductor testing device 1; and a plurality of delay generating sections 22-1 to 22-n for providing predetermined timings to pins of an LSI of the DUT 10 and the pattern comparator 13.
Among them, each of the delay generating sections 22-1 to 22-n has period calculation means 23 for calculating fraction data of a pattern period based on pattern period data (R1), and sending the fraction data in synchronization with period start data from an input terminal a0; delay calculation means 24 for adding up the fraction data from this period calculation means 23 and setting delay data (R2) to output integer data and fraction data; reference signal delaying means 310 for delaying a reference signal (reference clock) from the period generating section 21 by the integer data from this delay calculation means 24; and variable delaying means 320 for delaying the reference signal from the reference signal delaying means 310 by the fraction data from the delay calculation means 24 to output a timing pulse signal (e.g., see Japanese Patent Application Laid-Open No. 11-125660).
In this constitution, the timing generator 20 can generate the timing pulse signal delayed by a desired time to send the signal to the pattern comparator 13 or the like.
It is to be noted that, as shown in FIG. 6, a part which includes the period calculation means 23 and the delay calculation means 24 and which calculates a delay time of the reference signal is referred to as delay time calculation means A. Furthermore, a part which includes the reference signal delaying means 310 and the variable delaying means 320 and which delays the reference signal is referred to as a signal input/output circuit 300.
It is to be noted that, as shown in FIG. 6, a part which includes the period calculation means 23 and the delay calculation means 24 is referred to as delay time calculation means A which calculates a delay time of the reference signal. Furthermore, a part which includes the reference signal delaying means 310 and the variable delaying means 320 is referred to as a signal input/output circuit 300, which delays the reference signal.
FIG. 7 is a circuit diagram showing a condition in which this pattern-dependent jitter is generated. This drawing shows a circuit constitution of the signal input/output circuit 300 in which an input data signal (Data) is synchronized with a clock signal (Clock), further delayed by a predetermined time, and output to the outside.
This signal input/output circuit 300 will be further described. The circuit has a flip-flop 310 (corresponding to the reference signal delaying means 310 in FIG. 6) which outputs the input data signal (corresponding to the reference signal sent from the period generating section 21 to each of the delay generating sections 22-1 to 22-n in the conventional timing generator 20 (FIG. 6)) in accordance with an input timing of the clock signal (clock for counting an output timing); and a delaying circuit 320 (corresponding to the variable delaying means 320 in FIG. 6) which is connected to an output terminal side of the flip-flop 310 and which delays the output data signal by a predetermined time and then outputs the signal to the outside.
Assuming that the data signal has a random pattern (pattern in which a pulse wave is generated at random) and the clock signal has a continuous pattern (pattern in which the pulse wave is continuously generated in a certain period), the delaying circuit 320 is connected to a path (random pattern passage shown by C in FIG. 7) through which the pulse wave passes in the random pattern, and the pattern-dependent jitter is easily generated in the random pattern passage.
Here, the pattern-dependent jitter includes a short term jitter and a thermal drift jitter.
First, the short term jitter will be described. The short term jitter means that one edge (noted edge or subject edge) is influenced by a past edge to produce a fluctuation in a case where a plurality of pulse waves are generated.
For example, when the pulse wave is continuously generated as shown in FIG. 8(a), a noted edge (edge marked with ●) is influenced by a past edge (edge marked with ◯ in the pulse wave having the edge marked with ●, (1) of FIG. 8(a)) in the pulse wave having the noted edge, and edges (edges marked with ◯ in the past pulse wave other than the pulse wave having the edge marked with ●, FIGS. 8(a)(2), (3)) in the pulse wave generated in the past.
On the other hand, when the pulse wave is generated in the state of a single shot as shown in FIG. 8(b), the noted edge is mainly influenced by the past edge (edge marked with ◯) in the pulse wave having the noted edge (FIGS. 8(b)(1)).
In this case, another pulse wave is sometimes generated at random at the most recent time as viewed from the pulse wave having the noted edge, i.e., immediately prior to the noted edge. For example, when the pulse wave is generated at the most recent time, the noted edge is influenced by each edge of the past pulse wave in the same manner as in FIGS. 8(a)(2). On the other hand, when any pulse wave is not generated at this time, the edge is not influenced thereby (see FIGS. 8(b)(2), (3)).
Here, the edge influencing the noted edge in a case where the pulse wave is continuously generated is compared with the edge influencing the noted edge in a case where the pulse wave is generated in a manner of single eruption.
First, either of the past edges in the pulse waves having the noted edges have an influence in common (FIGS. 8(a)(1) and 8(b)(1)).
Next, the edge of the pulse wave, generated a certain time or more before the generation time of the noted edge, has some influence, but such influence is very small and can be ignored (FIGS. 8(a) (3) and 8(b) (3)).
Moreover, as to each edge in the pulse wave generated in a past time range in the vicinity of the generation time of the pulse wave having the noted edge, the influence of the edge differs in a case where the pulse wave is continuously generated and a case where the pulse wave is generated in the state of the single shot.
For example, in a case where the pulse wave is continuously generated, as shown in FIG. 8(a), each edge of the pulse wave generated in the past has a large influence on the noted edge (FIGS. 8(a)(2)).
On the other hand, in a case where the pulse wave is generated in the state of the single shot, the pulse wave has not been generated or has been generated in the past time range in the vicinity of the generation time of the pulse wave having the noted edge.
In a case where the pulse wave was generated in the past, the noted edge is largely influenced in the same manner as in a case where the pulse wave is continuously generated. On the other hand, when the pulse wave has not been generated, any pulse wave does not exist, and therefore the noted edge is not influenced as shown in FIG. 8(b).
Therefore, an influence exerted upon the noted edge in the continuous generation of the pulse wave differs from an influence exerted upon the noted edge in the single generation of the pulse wave in accordance with whether or not the pulse wave was generated in the past in a time range in the vicinity of the generation time of the pulse wave having the noted edge.
That is, in a case where the pulse wave is continuously generated, the pulse wave has been securely generated in the past time range in the vicinity of the generation time of the pulse wave having the noted edge, and the influences exerted upon the noted edge by the other edges are constant. Therefore, any short term jitter does not have to be considered in a path (continuous clock passage) through which the continuous pulse wave passes.
On the other hand, in a case where the pulse wave is generated in the state of the single shot, a degree of the influence differs whether or not the pulse wave has been generated in the past time range in the vicinity of the generation time of the pulse wave having the noted edge. That is, a pattern (FIG. 8(c)) influenced by the past edge, and a pattern (FIG. 8(d)) hardly influenced by the past edge are generated at random, and accordingly the influences are not constant. Therefore, in a path through which the pulse wave generated by the single shot passes (random pattern passage), the influence exerted upon the noted edge changes, and the pattern-dependent jitter (short term jitter) is generated.
Next, the thermal drift jitter will be described. The thermal drift jitter means that the fluctuation is generated in the waveform under the influence of a temperature change.
The delaying circuit 320 shown in FIG. 7 has, for example, the arbitrary number of (usually several tens to hundreds) inverters 321 shown in FIG. 9. When the number of the inverters 321 is increased, the delay time can be increased.
In each inverter 321 is provided with transistors 322 as shown in FIG. 9. In each transistor 322, the temperature changes with the generated pattern of the pulse wave, and a voltage between base and emitter (VBE) fluctuates.
In each inverter 321 is provided with transistors 322 as shown in FIG. 9. In each transistor 322, the temperature changes with the generated pattern of the pulse wave, and a voltage across the base and emitter (VBE) of the transistor fluctuates.
For example, in the continuous clock passage, since the pulse wave is continuously generated, the temperature change is substantially constant. On the other hand, in the random pattern passage, since the pulse wave is generated in the state of the single shot, the temperature change is not constant. Therefore, the voltage VBE fluctuates, a timing to output the signal changes, and the pattern-dependent jitter (thermal drift jitter) is generated. Especially, the larger the number of the inverters 321 are, the larger the thermal drift jitter becomes.
As described above, the conventional signal input/output circuit has had a situation in which the short term jitter or the thermal drift jitter may be generated. Therefore, the timing error has been generated in the output timing pulse signal in the timing generator provided with the signal input/output circuit. Moreover, for the semiconductor testing device using the timing generator, an accurate test result cannot be obtained because of the timing error.
Additionally, as shown in FIG. 9, the delaying circuit 320 usually has a plurality of inverters 321. Therefore, the pattern-dependent jitter is added up toward subsequent stages of the inverters 321, and the timing error of the timing pulse signal is further enlarged.
The present invention has been proposed in order to solve the problem of the above-described conventional technique, and an object thereof is to provide a timing generator and a semiconductor testing device in which pattern-dependent jitters are reduced to decrease timing errors of timing pulse signals in a timing generator so that a test timing in the semiconductor testing device can be inhibited from being displaced.